Read, program and erase operations in a memory occur during different memory modes. As a result, when a memory is being erased or programmed, the memory is not otherwise accessible for read operations. When a memory stores both program and data information, the memory is unavailable for code execution. The unavailability of the memory will starve an associated processor from vital information. A known solution to this problem is to implement a memory system with multiple separate memory arrays. Therefore, when one memory array is being programmed or erased, the other memory array is independently available. However, a significant disadvantage to this type of memory system exists. The use of separate memory arrays results in significantly more size and circuitry for the memory system because additional memory decoders, drivers and control circuitry are required. Such additional circuitry also results in a more expensive memory system. For example, the cost of implementing a separate block of EEPROM or small-sector FLASH to guarantee access to program memory is prohibitive. The result of this limitation is reduced system performance. When the program memory is not available, no interrupt servicing may occur in a memory system. As a result, system latency occurs and is dependent on the erase time of the memory which is typically slow for nonvolatile memory.